This invention relates to integrated circuits including an array of asymmetric cells, e.g. split gate floating gate memory devices such as EPROMs or EEPROMs, and more specifically to address decoder circuits for floating gate memory devices.
FIG. 1 illustrates an array 10 of split gate floating gate transistors including a group of control gates or word lines WL0 to WL3, a group of source/drain regions or bit lines BL0 to BL9, and a group of floating gates FG1 to FG36. Although FIG. 1 only illustrates four word lines, ten bit lines and 36 floating gates, typical floating gate memory arrays comprise a much larger number of word lines, bit lines and floating gates. The transistors of array 10 are asymmetric, i.e. the floating gates cover a portion of the channel adjacent to the transistor drain but not adjacent to the transistor source.
Array 10 employs a "virtual ground" architecture. This means that bit line BL1 is used as a drain when it is desired to read or program the state of floating gates FG1, FG10, FG19 and FG28, but is used as a source when it is desired to read or program the state of floating gates FG2, FG11, FG20 and FG29. Similarly, the other bit lines in array 10 are used as either source regions or drain regions, depending upon whether it is desired to read or program the state of a transistor immediately to the right or immediately to the left of the bit line. Virtual ground memory devices are discussed, for example, in U.S. Pat. No. 4,409,723 issued to Eliyahou Harari on Oct. 18, 1983 and incorporated herein by reference.
FIG. 2 schematically illustrates a portion of array 10 and bit line decode circuit 11 for coupling a first one of the bit lines to ground and a second one of the bit lines to a sense amplifier SA. The bit lines are organized into groups of eight, each group being coupled to an associated predecode multiplexer 12, each predecode multiplexer being coupled to a second decode multiplexer 13. As can be seen, bit lines BL0 to BL7 can each be coupled to a lead L1-1 via transistors Q-1-0 to Q-1-7, respectively, and lead L1-1 can be coupled to ground via a transistor QA. Similarly, bit lines BL1 to BL8 can be coupled to a line L2-1 via transistors Q-2-1 to Q-2-8 respectively, which in turn can be coupled to sense amplifier SA via a transistor QB. Transistors Q-1-0 to Q-1-7 and Q-2-1 to Q-2-8 are part of a first one of predecoder multiplexers 12.
Bit lines BL8 to BL15 are coupled to a line L1-2 via transistors Q-1-8 to Q-1-15, respectively (within a second one of multiplexers 12), which in turn is coupled to ground via a transistor QC (within multiplexer 13). Similarly, bit lines BL9 to BL16 are coupleted to a line L2-2 via transistors Q-2-9 to Q-2-16 (part of the second one of multiplexers 12) which in turn is coupled to sense amplifier SA via a transistor QD. Thus, it is seen that every eighth bit line, starting with bit line BL8, is coupled to ground via a first one of predecode multiplexers 12 and to sense amplifier SA via a second one of predecode multiplexers 12. Multiplexers 12 are controlled by signals Y0 to Y7 decoded from EPROM column address lines A0 to A2 (not shown). Multiplexer 13 is controlled by the other EPROM column address lines.
It would be desirable to reduce the size of array 10. One method of doing this would be to move the word lines closer to each other, e.g. moving word line WL0 closer to word line WL1 (see FIG. 1). This would entail either moving floating gates FG1 to FG9 closer to floating gates FG10 to FG18, or making the floating gates narrower. Unfortunately, design considerations dictate that a certain amount of space be left between the floating gates and that the floating gates be a certain width. These design considerations are described in U.S. Pat. application Ser. No. 07/258,952, filed 10/17/88, entitled "Split Gate Memory Array Having Staggered Floating Gate Rows and Method For Making Same", filed by Boaz Eitan and Reza Kazerounian on the same day as the present Application, and incorporated herein by reference.
Briefly, the major factors governing the width of the transistor cell are as follows:
1. Each transistor must have a channel sufficiently wide to conduct an appropriately large read current. PA1 2. Each floating gate must overlap the "bird's beak" formed at the periphery of field oxide FOX. (Field oxide FOX is placed between the various floating gates to prevent parasitic channels from forming between adjacent transistors.) The bird's beak is describe in the above-incorporated Eitan et al. application. PA1 3. A certain amount of space must be left between adjacent floating gates so that the floating gates may be defined properly without contacting one another.
One method of reducing the transistor cell widths is to stagger the floating gates, e.g., as in array 20 illustrated in FIG. 3. Thus, instead of being placed directly adjacent bit line BL2, floating gate FG5 is placed directly adjacent bit line BL1 while floating gate FG2, formed in the same column of transistor as floating gate FG5, is directly adjacent bit line BL2.
For reasons described in detail in the above-incorporated Eitan et al. application, staggering the floating gates eliminates the need for providing field oxide FOX, and thus, the floating gates do not have to overlap a "bird's beak" region of field oxide.
A staggered floating gate arrangement also permits a reduction in the length of each cell by permitting a reduction in the width of each bit line. In array 10, if the bit lines are self-aligned with the floating gates (see U.S. Pat. No. 4,639,893, issued to Eitan and incorporated herein by reference), and the floating gates are misaligned in direction A (see FIG. 1), the effective width of each bit line will be reduced and the bit line resistance will be increased. In order to ensure that the bit line resistance is below a certain maximum value, the width of the bit line mask is enhanced in the prior art. However, in array 20, if the floating gates are misaligned and placed too far to the right, an increase in the resistance along a first portion of the bit lines (such as portion P1) will be partially offset by a decrease in the resistance along a second portion of the bit lines (such as portion P2). Therefore, the bit line resistance in array 20 is less sensitive to floating gate misalignment than the bit line resistance of array 10, and thus array 20 can be formed with narrower bit lines and a smaller cell pitch.
Lastly, during the polysilicon etching step which defines the individual floating gates, the corners of the floating gates are rounded, thereby effectively increasing the distance between the resulting floating gates. This permits the floating gate mask window regions to be closer to one another when manufacturing array 20 than when manufacturing array 10.
In array 20, when it is desired to read (or program) the state of a first group of floating gates within a first column of transistors (e.g., floating gates FG2 and FG10 in column C1), bit line BL2 serves as a drain and bit line BL1 serves as a source, whereas when it is desired to read (or program) the state of a second group of floating gates (such as floating gates FG5 and FG13 in column C1), bit line BL1 serves as a drain and bit line BL2 serves as the source. Thus, unlike the decoder used in conjunction with array 10, a decoder used in conjunction with array 20 must be capable of causing the bit lines to function as either sources or drains depending on the word line being addressed.
During read operations, a dummy transistor from a column of dummy transistors is coupled to a sense amplifier so that the drain voltage of the transistor being read can be compared with the drain voltage of the dummy transistor. It would be desirable to ensure that the transistor selected from the dummy column has its floating gate on the same side of the channel as the transistor being read, so that the selected dummy transistor and the transistor being read have comparable electrical characteristics. Also, since some dummy transistors have their floating gates on one side of the transistor cell, while other dummy transistors have their floating gates on the other side of the transistor cell, the bit line decoder should be capable of coupling each dummy bit line to the ground and to the sense amplifier.
It is desirable to provide redundant rows for replacing defective rows within the EPROM array. It would be desirable to construct the decoder so that each redundant row can replace any row in the array, regardless of whether the replaced row has its floating gates on the left side or right side of the cell.